| Summary: | The development of a Smart Grid system is aimed at improving the reliability of the aging electrical grid. As an enabler of this technology, a network of ultra low power 2x2mm sensor node for real time and perpetual monitoring of high voltage transmission line current using CMOS65 technology is proposed. It uses energy harvesting from power lines and on-chip regulation. This however, results in a noisy supply voltage of 0.5V with a 100mV ripple. Coupled with process variation and a wide temperature range of 0-120˚C, this provides design challenges in developing the transceiver for the sensor node. This work is focused on the design methodology of the 450 kHz BPSK Analog Front End for Powerline Communications. Transmitter and receiver specifications for achieving the target bit error rate were derived using a Matlab model of the digital demodulator and coupler to a single wire without interferences. To achieve the requirements under the given conditions, the transmitter makes use of a class D topology to take advantage of its railed input together with low V_th transistors for high rebustness to process, temperature, and supply variations. On the other hand, the receiver used a shunt feedback amplifier to maximize matching and limit the bandwidth. The g_m-stage makes use of a full differential common source with a resistive common mode feedback to increase power supply rejection while limiting device stacks to two for linearity. Two stages were used to increase loop gain at a low supply. Using a modeled 1 MHz 450-550mV rippling supply, and across the entire range of variations, at the specified power budget of 2.5mW, the transmitter achieved 300μW - 700μW of output power, 4-12% THD, and a maximum of 3.54% phase distortion. This allowed the receiver to have the worst case sensitivity of -33dBm and achieve maximum of 4.9% phase distortion and 50dB dynamic range that is more than enough for the target bit rate while limiting the power consumption to the specified 500μW. At the same time, the input impedance was optimized to 200Ω-300Ω. Additionally, both designs were characterized with an actual DC-DC converter.
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