Digital system test and testable design using HDL models and architectures - Navabi, Zainalabedin; SpringerLink (Online service). (Boston, MA Springer US Imprint: Springer, 2011)
Digital System Test and Testable Design: Using HDL Models and Architectures by: Zainalabedin Navabi This book is about digital system test and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware / software environment facilitates description of complex test programs and test strategies. Combines design and test Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulate Simulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patterns Describes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methods Virtual testers (Verilog testbenches) play the role of ATEs for driving scan tests and examining the circuit under test Verilog descriptions of scan designs and BIST architectures are available that can be used in actual designs PLI test utilities developed in-text are available for download Introductory Video for Verilog basics, software developed in-text, and PLI basics available for download Powerpoint slides available for each chapter
Note continued: 2.8.3. Simple Sequential Testbench -- 2.8.4. Limiting Data Sets -- 2.8.5. Synchronized Data and Response Handling -- 2.8.6. Random Time Intervals -- 2.8.7. Text IO -- 2.8.8. Simulation Code Coverage -- 2.9. PLI Basics -- 2.9.1. Access Routines -- 2.9.2. Steps for HDL/PLI Implementation -- 2.9.3. Fault Injection in the HDL/PLI Environment -- 2.10. Summary -- References -- 3. Fault and Defect Modeling -- 3.1. Fault Modeling -- 3.1.1. Fault Abstraction -- 3.1.2. Functional Faults -- 3.1.3. Structural Faults -- 3.2. Structural Gate Level Faults -- 3.2.1. Recognizing Faults -- 3.2.2. Stuck-Open Faults -- 3.2.3. Stuck-at-0 Faults -- 3.2.4. Stuck-at-1 Faults -- 3.2.5. Bridging Faults -- 3.2.6. State-Dependent Faults -- 3.2.7. Multiple Faults -- 3.2.8. Single Stuck-at Structural Faults -- 3.2.9. Detecting Single Stuck-at Faults -- 3.3. Issues Related to Gate Level Faults -- 3.3.1. Deteeting Bridging Faults -- 3.3.2. Undetectable Faults -- 3.3.3. Redundant Faults -- 3.4. Fault Collapsing -- 3.4.1. Indistinguishable Faults -- 3.4.2. Equivalent Single Stuck-al Faults -- 3.4.3. Gate-Oriented Fault Collapsing -- 3.4.4. Line-Oriented Fault Collapsing -- 3.4.5. Problem with Reconvergenl Fanouts -- 3.4.6. Dominance Fault Collapsing -- 3.5. Fault Collapsing in Verilog -- 3.5.1. Verilog Testbench for Fault Collapsing -- 3.5.2. PLI Implementation of Fault Collapsing -- 3.6. Summary -- References -- 4. Fault Simulation Applications and Methods -- 4.1. Fault Simulation -- 4.1.1. Gate-Level Fault Simulation -- 4.1.2. Fault Simulation Requirements -- 4.1.3. HDL Environment -- 4.1.4. Sequential Circuit Fault Simulation -- 4.1.5. Fault Dropping -- 4.1.6. Related Terminologies -- 4.2. Fault Simulation Applications -- 4.2.1. Fault Coverage -- 4.2.2. Fault Simulation in Test Generation --Note continued: 4.2.3. Fault Dictionary Creation -- 4.3. Fault Simulation Technologies -- 4.3.1. Serial Fault Simulation -- 4.3.2. Parallel Fault Simulation -- 4.3.3. Concurrent Fault Simulation -- 4.3.4. Deductive Fault Simulation -- 4.3.5. Comparison of Deductive Fault Simulation -- 4.3.6. Critical Path Tracing Fault Simulation -- 4.3.7. Differential Fault Simulation -- 4.4. Summary -- References -- 5. Test Pattern Generation Methods and Algorithms -- 5.1. Test Generation Basics -- 5.1.1. Boolean Difference -- 5.1.2. Test Generation Process -- 5.1.3. Fault and Tests -- 5.1.4. Terminologies and Definitions -- 5.2. Controllability and Observability -- 5.2.1. Controllability -- 5.2.2. Observability -- 5.2.3. Probability-Based Controllability and Observability -- 5.2.4. SCOAP Controllability and Observability -- 5.2.5. Distances Based -- 5.3. Random Test Generation -- 5.3.1. Limiting Number of Random Tests -- 5.3.2. Combinational Circuit RTG -- 5.3.3. Sequential Circuit RTG -- 5.4. Summary -- References -- 6. Deterministic Test Generation Algorithms -- 6.1. Deterministic Test Generation Methods -- 6.1.1. Two-Phase Test Generation -- 6.1.2. Fault-Oriented TG Basics -- 6.1.3. D-Algorithm -- 6.1.4. PODEM (Path-Oriented Test Generation) -- 6.1.5. Other Deterministic Fault-Oriented TG Methods -- 6.1.6. Fault-Independent Test Generation -- 6.2. Sequential Circuit Test Generation -- 6.3. Test Data Compaction -- 6.3.1. Forms of Test Compaction -- 6.3.2. Test Compatibility -- 6.3.3. Static Compaction -- 6.3.4. Dynamic Compaction -- 6.4. Summary -- References -- 7. Design for Test by Means of Scan -- 7.1. Making Circuits Testable -- 7.1.1. Tradeoffs -- 7.1.2. Testing Sequential Circuits -- 7.1.3. Testability of Combinational Circuits -- 7.2. Testability Insertion -- 7.2.1. Improving Observability -- Note continued: 7.2.2. Improving Controllability -- 7.2.3. Sharing Observability Pins -- 7.2.4. Sharing Control Pins -- 7.2.5. Reducing Select Inputs -- 7.2.6. Simultaneous Control and Observation -- 7.3. Full Scan DFTTechnique -- 7.3.1. Full Scan Insertion -- 7.3.2. Flip-Flop Structures -- 7.3.3. Full Scan Design and Test -- 7.4. Scan Architectures -- 7.4.1. Full Scan Design -- 7.4.2. Shadow Register DFT -- 7.4.3. Partial Scan Methods -- 7.4.4. Multiple Scan Design -- 7.4.5. Other Scan Designs -- 7.5. RT Level Scan Design -- 7.5.1. RTL Design Full Scan -- 7.5.2. RTL Design Multiple Scan -- 7.5.3. Scan Designs for RTL -- 7.6. Summary -- References -- 8. Standard IEEE Test Access Methods -- 8.1. Boundary Scan Basics -- 8.2. Boundary Scan Architecture -- 8.2.1. Test Access Port -- 8.2.2. Boundary Scan Registers -- 8.2.3. TAP Controller -- 8.2.4. Decoder Unit -- 8.2.5. Select and Other Units -- 8.3. Boundary Scan Test Instructions -- 8.3.1. Mandatory Instructions -- 8.4. Board Level Scan Chain Structure -- 8.4.1. One Serial Scan Chain -- 8.4.2. Multiple-Scan Chain with One Control Test Port -- 8.4.3. Multiple-Scan Chains with One TDI, TDO but Multiple TMS -- 8.4.4. Multiple-Scan Chain, Multiple Access Port -- 8.5. RT Level Boundary Scan -- 8.5.1. Inserting Boundary Scan Test Hardware for CUT -- 8.5.2. Two Module Test Case -- 8.5.3. Virtual Boundary Scan Tester -- 8.6. Boundary Scan Description Language -- 8.7. Summary -- References -- 9. Logic Built-in Self-test -- 9.1. BIST Basics -- 9.1.1. Memory-based BIST -- 9.1.2. BIST Effectiveness -- 9.1.3. BISTTypes -- 9.1.4. Designing a BIST -- 9.2. Test Pattern Generation -- 9.2.1. Engaging TPGs -- 9.2.2. Exhaustive Counters -- 9.2.3. Ring Counters -- 9.2.4. Twisted Ring Counter -- 9.2.5. Linear Feedback Shift Register -- Note continued: 9.3. Output Response Analysis -- 9.3.1. Engaging ORAs -- 9.3.2. One's Counter -- 9.3.3. Transition Counter -- 9.3.4. Parity Checking -- 9.3.5. Serial LFSRs (SISR) -- 9.3.6. Parallel Signature Analysis -- 9.4. BIST Architectures -- 9.4.1. BTST-related Terminologies -- 9.4.2. Centralized and Separate Board-level BIST Architecture (CSBL) -- 9.4.3. Built-in Evaluation and Self-test (BEST) -- 9.4.4. Random Test Socket (RTS) -- 9.4.5. LSSD On-chip Self Test -- 9.4.6. Self-testing Using MTSR and SRSG -- 9.4.7. Concurrent BIST -- 9.4.8. BILBO -- 9.4.9. Enhancing Coverage -- 9.5. RT Level BIST Design -- 9.5.1. CUT Design, Simulation, and Synthesis -- 9.5.2. RTS BIST Insertion -- 9.5.3. Configuring the RTS BIST -- 9.5.4. Incorporating Configurations in BIST -- 9.5.5. Design of STUMPS -- 9.5.6. RTS and STUMPS Results -- 9.6. Summary -- References -- 10. Test Compression -- 10.1. Test Data Compression -- 10.2. Compression Methods -- 10.2.1. Code-based Schemes -- 10.2.2. Scan-based Schemes -- 10.3. Decompression Methods -- 10.3.1. Decompression Unit Architecture -- 10.3.2. Cyclical Scan Chain -- 10.3.3. Code-based Decompression -- 10.3.4. Scan-based Decompression -- 10.4. Summary -- References -- 11. Memory Testing by Means of Memory BIST -- 11.1. Memory Testing -- 11.2. Memory Structure -- 11.3. Memory Fault Model -- 11.3.1. Stuck-At Faults -- 11.3.2. Transition Faults -- 11.3.3. Coupling Faults -- 11.3.4. Bridging and State CFs -- 11.4. Functional Test Procedures -- 11.4.1. March Test Algorithms -- 11.4.2. March C-Algorithm -- 11.4.3. MATS+Algorithm -- 11.4.4. Other March Tests -- 11.5. MBIST Methods -- 11.5.1. Simple March MBIST -- 11.5.2. March C- MBIST -- 11.5.3. Disturb MBIST -- 11.6. Summary -- References
Electronic reproduction.
Keywords: Digital integrated circuits -- Testing; Digital integrated circuits -- Design and construction; Verilog (Computer hardware description language).; Electronic books