Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache
With multicore technology becoming more ubiquitous, there is an increasing importance to improve the performance of memory hierarchy so as to close the gap between processor and memory performance known as the memory wall. An opportunity for improving memory hierarchy performance is by reducing the...
| Prif Awdur: | |
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| Fformat: | Traethawd Ymchwil |
| Iaith: | English |
| Cyhoeddwyd: |
Quezon City
College of Engineering, University of the Philippines Diliman
2013
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| Pynciau: |