Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache - Dioquino, Darryl Aldrin M. (College of Engineering, University of the Philippines Diliman, 2013)
With multicore technology becoming more ubiquitous, there is an increasing importance to improve the performance of memory hierarchy so as to close the gap between processor and memory performance known as the memory wall. An opportunity for improving memory hierarchy performance is by reducing the misses in on-chip last level caches (L2 and beyond) since a miss in those memories means off-chip prefetches that take hundreds of processor cycles to finish. Traditionally, LRU policy is used to manage blocks in cache memories. LRU manages blocks efficiently in L1 because of the abundance of locality for that level. However, locality is not as abundant in higher level caches as the more temporal blocks get filtered in the L1. LRU suffers from this reduced locality because it tends to keep blocks longer than it should instead of allocating the space for other blocks that would be usefully kept. This problem is aggravated in multiprocessor systems since LRU tends to keep data invalidated by coherence protocols. Invalid data never contribute a hit and only waste space in the cache. This thesis studies the integration of Less-Reused Filtering (LRF) and Live Time Prediction (LvP) schemes with a modified LRU replacement (LRU-Inv) as alternative policies for LRU in the context of multiprocessors with a shared L2 cache that does not enforce inclusion. It is assumed that the L2 is the last level on-chip cache. The miss rates of the proposed schemes are compared with LRU and LRU-Inv replacements for a subset of SPLASH-2 benchmarks. For benchmarks with miss rates greater than 15% in a 1MB 8-way associative LRU cache, results show that LvP with LRU-Inv can reduce the miss rates by as much as 30.14% compared to LRU. However, it is not as effective against LRU-Inv and can increase the miss rates of LRU-Inv by as much as 9.35%. LRF with LRU-Inv, on the other hand is effective against LRU and LRU-Inv and can reduce their miss rates by as much as 43.34% and 19.26% respectively. For a 9-way LRU-Inv cache howeverm SLRF-Inv performs better for other benchmarks while it performs worse for others. SLRF-Inv was able to reduce the miss rate of the 9-way LRU-Inv cache by as much as 11.82%. However, it also increased the miss rate for a program by as much as 55.56%.