Integrated controller techniques for flash memories - Abadies, Hearty Z. (Quezon City College of Engineering, University of the Philippines Diliman, 2013)
The flash memory is becoming the preferred non-vloatile memory of choice because of its low-power, high density, and robustness. However, it (1) does not support in-place updates, (2) is sensitive to read, write, and erase disturbs, (3) has limited P/E cycles, and (4) has lower access speed when compared to DRAM. These drawbacks lead to a slower flash memory with a short lifespan. To mitigate these drawbacks, various flash controller techniques are developed. Hence, this thesis integrates four different techniques in a flash controller to study their effects on the flash memory performance. The proposed flash controller implements the following techniques: (1) a split cache memory management technique to address the architectural level issues of the flash memory; (2) wear levelling and garbage collection techniques to spread the wear of flash memory cells; (3) a density alteration technique to mitigate effects of the flash memory cell aging; and (4) a Reed-Solomon (RS) error correction technique to correct erroneous bits in the stored data. These techniques are geared toward improving the reliability and lifetime of the flash memory. Apart from the RS code, all techniques are modelled and simulated in MATLAB. The RS code is implemented in a 65nm CMOS technology. Each technique is characterized individually then integrated. Overall, the proposed controller increased the lifespan of the flash memory by two ordes of magnitude when compared to a flash memory with a 2 ECC simple controller. However, this improvement results in 4.1X increase in memory latency.
Thesis (M.S. Electrical Engineering)--University of the Philippines, Diliman.
Keywords: Flash memories (Computers).; Flash controller techniques