A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design

Research shows that the bulk of power consumption of a processor system goes to the cache memory of the processor. The two most common techniques in reducing the power consumption of the cache memory are cache sub-banking and block buffering. However, these techniques have only been applied to singl...

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主要作者:	Zarsuela, Jestoni V.
格式:	Thesis
語言:	English
出版:	2010.
主題:	Electric power consumption. Cache memory. VHDL (Computer hardware description language). Cache sub-ranking technique. Block buffering technique. Cache memory power reduction technique. Register Transfer Level (RTL) models.