A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design

Research shows that the bulk of power consumption of a processor system goes to the cache memory of the processor. The two most common techniques in reducing the power consumption of the cache memory are cache sub-banking and block buffering. However, these techniques have only been applied to singl...

詳細記述

書誌詳細

第一著者:	Zarsuela, Jestoni V.
フォーマット:	学位論文
言語:	English
出版事項:	2010.
主題:	Electric power consumption. Cache memory. VHDL (Computer hardware description language). Cache sub-ranking technique. Block buffering technique. Cache memory power reduction technique. Register Transfer Level (RTL) models.