A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design - Zarsuela, Jestoni V.
Research shows that the bulk of power consumption of a processor system goes to the cache memory of the processor. The two most common techniques in reducing the power consumption of the cache memory are cache sub-banking and block buffering. However, these techniques have only been applied to single processor systems. Thus, the purpose of this study is to introduce these two techniques to multiprocessor systems. Parallel execution will be the biggest issue that will affect the behavior of the cache sub-banking and block buffering techniques. Previous research claimed that the execution of a program spread between more than one processor tends to decrease its locality of reference compared to the same program executing on one processor. RTL models of cache architectures implementing the cache sub-banking and the block buffering techniques on a multiprocessor environment are presented. Memory traces were gathered from the M5 simulator that was run o SPLASH-2 benchmark. This benchmark served as the test bench for the RTL models. The block buffering technique was shown to be inefficient when applied to the level two cache memory. Thus, it was removed in the research design. It also found out that a higher degree of set associativity for the level two cache memory translates to a higher level of performance, while having a large number of sets produces a more power-efficient cache architecture. The application of cache sub-banking technique resulted to an average power reduction of 85.18% and a negligible area overhead.