A 10MHz 3rd order Butterworth Gm-C low-pass filter in a 90nm CMOS process - Almazan, Sherwin Paul Roldan
A number of design issues and challenges entailed by CMOS scaling motivate extensive research in transceivers design at the nano-scale. One of the critical blocks of an RF transceivers is the low-pass filters (LPF) as it is responsible for isolating the baseband signal, which carries the information from out-of-band interference. Through the years, a number of techniques in active filter design have been published. In spite of this, the effectiveness of these filter design techniques at the nanometer scale, where short channel effects of transistors are dominant and unpredictable , have yet to be investigated. This research aims to design a 3rd order Butterworth gm -C LPF for 10 MHz applications using a 90 mm CMOS process. Due to its robustness to process parameter tolerances, an LC-ladder filter prototype is emulated using two design methodologies the (1) element replacement (ER) and the (2) signal flow graph (SFG) methods. As a basic building block of the LPF, an operational transconductance amplifier (OTA) that is based on bias-offset cross-coupled differential pairs is also designed and characterized. With this OTA's property of having its transconductance linearly controlled by a DC voltage bias, the corner frequency of the filter could be externally turned to achieve the 10Mhz specifications for bandwidth .Meanwhile, to attain good output matching and to drive the impedance of the test equipment, a source follower is attached to the LPF output. Simulation results show that the two gm -C LPF circuits achieved the 10 MHz bandwidth target and exhibited frequency tuning through DC voltage bias variation. However, the LPF designed using the SFG method attained a much higher DC gain which is critical when integrating the LPF with the other receiver blocks. Note that apart from achieving lower noise figure for the entire receiver system, a higher LPF gain ensures that the amplitude of its output baseband signal is way above the sensitivity level of the next stage. Moreover, the LPF using the SFG method slightly has better performance in terms of linearity and noise, and has a more stable and robust frequency response. Thus the LPF, designed using the SFG method is the circuit chosen for fabrication. Setting Vin (DC)= Vc = 0.65 V and Vb1= Vb2 = 0.5V and after de-embedding is performed, on-wafer test measurements of the fabricated LPF using the SFG method show that a low frequency gain of -11.574db and a bandwidth of 9.318Mhz is achieved. The HD2 at 50mV peak and 1MHz input is around -25dBc, while the power consumption is 4.122mW. This thesis is the first in the laboratory to embark on the design of the monolithic active filters. The knowledge gain from this study is envisioned to help researchers in the laboratory in building a fully integrated CMOS transceivers in future work.