System-level analog architecture design for WiMAX direct-conversion receivers in 90nm CMOS - Alunan, Lendl Israel Makabenta
Recent advances in wireless communications schemes have resulted in an increasing demand for small, highly integrated RF transceivers that have very low power dissipation. Consequently, there has been an aggressive downscaling of RF CMOS technologies, enabling the possibility of denser integration, higher transit frequencies, and lower costs. However, CMOS scaling has introduced new design challenges. Complex systems such as wireless receivers could no longer be analyzed simply at the circuit level. There arises a need to simulate new architectures at a higher level of abstraction so they can be optimized and compared quantitatively in terms of performance, power and area. There exist a large dependency between system-level architectural decisions and performance metrics of each circuit block in the architecture, which is turn dictated by the technology processed being used. In this research, the different system-level issues involved in the design of a direct-conversion receiver are investigated. The receiver is designed to target Worldwide Interoperability for Microwave Access (WiMAX). Applications, which has been rapidly gaining momentum as an alternative to cable and DSL in delivering wireless broadband access to end-users. It was found through simulations that the CMOS process introduces large values of flicker noise, which could be a barrier especially for the design of the downconversion. High-level design trade-offs in the direct-conversion receiver architecture are also investigated to characterize the effect of each block in the whole system's performance. Based on system-level simulations, a design flow is developed that would further improve subsequent efforts to design a fully integrated wireless CMOS transceiver, in the laboratory.