कवर छवि

Random access at double the speed.

Unveiled at the IEEE's Symposium on VLSI Circuits, a novel dynamic memory architecture challenges static memory.

ग्रंथसूची विवरण
में प्रकाशित:IEEE spectrum 39, 8(duplicate) (2002).
मुख्य लेखक: Geppert, N.
स्वरूप: लेख
भाषा:अंग्रेज़ी
विषय:
512 Kbit.
ASIC.
IBM demonstration chip.
Architectural device.
Circuit blocks.
Dynamic memory architecture.
Embedded DRAM.
Macros.
On-chip memory applications.
Systems-on-chip.
Write-back buffer.