Random access at double the speed.

Random access at double the speed.

Taispeáin gach leagan (3)

Unveiled at the IEEE's Symposium on VLSI Circuits, a novel dynamic memory architecture challenges static memory.

Sonraí bibleagrafaíochta
Foilsithe in:IEEE spectrum 39, 8(duplicate) (2002).
Príomhchruthaitheoir: Geppert, N.
Formáid: Alt
Teanga:English
Ábhair:
512 Kbit.
ASIC.
IBM demonstration chip.
Architectural device.
Circuit blocks.
Dynamic memory architecture.
Embedded DRAM.
Macros.
On-chip memory applications.
Systems-on-chip.
Write-back buffer.