Random access at double the speed.

Random access at double the speed.

Show all versions (3)

Unveiled at the IEEE's Symposium on VLSI Circuits, a novel dynamic memory architecture challenges static memory.

Bibliographic Details
Published in:IEEE spectrum 39, 8(duplicate) (2002).
Main Author: Geppert, N.
Format: Article
Language:English
Subjects:
512 Kbit.
ASIC.
IBM demonstration chip.
Architectural device.
Circuit blocks.
Dynamic memory architecture.
Embedded DRAM.
Macros.
On-chip memory applications.
Systems-on-chip.
Write-back buffer.