Random access at double the speed.

Unveiled at the IEEE's Symposium on VLSI Circuits, a novel dynamic memory architecture challenges static memory.

Bibliografiset tiedot

Julkaisussa:	IEEE spectrum 39, 8(duplicate) (2002).
Päätekijä:	Geppert, N.
Aineistotyyppi:	Artikkeli
Kieli:	English
Aiheet:	512 Kbit. ASIC. IBM demonstration chip. Architectural device. Circuit blocks. Dynamic memory architecture. Embedded DRAM. Macros. On-chip memory applications. Systems-on-chip. Write-back buffer.