Random access at double the speed.

Random access at double the speed.

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Unveiled at the IEEE's Symposium on VLSI Circuits, a novel dynamic memory architecture challenges static memory.

Bibliografiska uppgifter
I publikationen:IEEE spectrum 39, 8(duplicate) (2002).
Huvudupphovsman: Geppert, N.
Materialtyp: Artikel
Språk:English
Ämnen:
512 Kbit.
ASIC.
IBM demonstration chip.
Architectural device.
Circuit blocks.
Dynamic memory architecture.
Embedded DRAM.
Macros.
On-chip memory applications.
Systems-on-chip.
Write-back buffer.