A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect. - Azadpour, M.A.
Due to decreasing device sizes and increasing clock speed, interconnect inductance is becoming an important factor in the on-chip delay analysis of deep submicrometer technologies. This delay has been represented as an RC model in the available electric design automation tools. In this paper, we model the on-chip interconnect as a RLC for systems running at multigigahertz frequencies. A static-extraction analysis method optimized for ASICs is detailed. It considers all the lines within the vicinity of the target signal line as return paths.
Keywords: RC model; RLC; Clock interconnect extractor; Clock interconnect optimization; Design optimization; Electric design automation; Inductance effect; Interconnect inductance; On-chip delay analysis; On-chip interconnect; Static-extraction analysis