Fixed-outline floorplanning enabling hierarchical design.

Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant t...

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Bibliografische gegevens
Gepubliceerd in:	IEEE Transactions on VLSI systems 11, 6 (2003).
Hoofdauteur:	Adya, S.N
Formaat:	Artikel
Taal:	English
Onderwerpen:	37 min. ASIC. Parquet-l. SoC. Application specific integrated circuits. Computation time. Fixed-outline floorplanning. Floorplan slack. Floorplanner implementation. Hierarchical design. Hierarchical paradigm. Optimization. Sequence pair. Simulated annealing. Slack computation. System on chip.