APA (7th ed.) Citation

Adya, S. Fixed-outline floorplanning: Enabling hierarchical design. IEEE Transactions on VLSI systems.

Chicago Style (17th ed.) Citation

Adya, S.N. "Fixed-outline Floorplanning: Enabling Hierarchical Design." IEEE Transactions on VLSI Systems .

MLA (9th ed.) Citation

Adya, S.N. "Fixed-outline Floorplanning: Enabling Hierarchical Design." IEEE Transactions on VLSI Systems, .

Warning: These citations may not always be 100% accurate.