Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect.

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect.

We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is silicon-on-insulator (SOI). SOI devices exhibit an effect known as parasitic bipolar effect (PBE), which can lead to incorrect logic values in the circui...

Mô tả đầy đủ

Chi tiết về thư mục
Xuất bản năm:IEEE Transactions on VLSI systems 11, 6 (2003).
Tác giả chính: Karandikar, S.K
Định dạng: Bài viết
Ngôn ngữ:English
Những chủ đề:
CMOS domino logic.
MOS discharge transistors.
SOI devices.
SOI domino logic incorporating solutions.
Si.
Parasitic bipolar effects.
Random logic gate network.
Silicon-on-insulator.
Technology mapping algorithm.
Transistor reordering.