Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect.

We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is silicon-on-insulator (SOI). SOI devices exhibit an effect known as parasitic bipolar effect (PBE), which can lead to incorrect logic values in the circui...

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में प्रकाशित:	IEEE Transactions on VLSI systems 11, 6 (2003).
मुख्य लेखक:	Karandikar, S.K
स्वरूप:	लेख
भाषा:	English
विषय:	CMOS domino logic. MOS discharge transistors. SOI devices. SOI domino logic incorporating solutions. Si. Parasitic bipolar effects. Random logic gate network. Silicon-on-insulator. Technology mapping algorithm. Transistor reordering.