00000cab a22000003a 4500 UP-99796217609624655 Buklod 20231007234420.0 m |o d | ta 110119s xx d | ||r ||||| || DENGII eng Karandikar, S.K. Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect. pp. 1094-1105 We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is silicon-on-insulator (SOI). SOI devices exhibit an effect known as parasitic bipolar effect (PBE), which can lead to incorrect logic values in the circuit. Our algorithm solves the technology mapping problem by permitting several transformations during the mapping process in order to avoid PBE, such as transistor reordering, altering the way that transistors are organized into gates, and adding pMOS discharge transistors. We minimize the total cost of implementation, which includes discharge transistors required for correct functioning. Our algorithm generates solutions that reduce the number of discharge transistors required by 53% and reduces the size of the final solution by 6.3% on average. We compare our results with a modification of a current technology mapping algorithm for bulk CMOS domino logic that reduces the cost of the final solution and find that our algorithm outperforms this method. CMOS domino logic. MOS discharge transistors. SOI devices. SOI domino logic incorporating solutions. Si. Parasitic bipolar effects. Random logic gate network. Silicon-on-insulator. Technology mapping algorithm. Transistor reordering. IEEE Transactions on VLSI systems 11, 6 (2003). FO UPD DENG-II Article