00000cab a22000003a 4500 UP-99796217609624630 Buklod 20231007234420.0 m |o d | ta 110119s xx d | ||r ||||| || DENGII eng Mansour, M.M. High-throughput LDPC decoders. pp. 976-996 A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design-namely LDPC code design, decoding algorithm, and decoder architecture. First, the interconnect complexity problem of current decoder implementations is mitigated by designing architecture-aware LDPC codes having embedded structural regularity features that result in a regular and scalable message-transport network with reduced control overhead. Second, the memory overhead problem in current day decoders is reduced by more than 75% by employing a new turbo decoding algorithm for LDPC codes that removes the multiple checkto-bit message update bottleneck of the current algorithm. A new merged-schedule merge-passing algorithm is also proposed that reduces the memory overhead of the current algorithm for low to moderate-throughput decoders. Moreover, a parallel soft-input-soft-output (SISO) message update mechanism is proposed that implements the recursions of the Balh-Cocke-Jelinek-Raviv (BCJR) algorithm in terms of simple "max-quartet" operations that do not require lookup-tables and incur negligible loss in performance compared to the ideal case. Finally, an efficient programmable architecture coupled with a scalable and dynamic transport network for storing and routing messages is proposed, and a full-decoder architecture is presented. Simulations demonstrate that the proposed architecture attains a throughput of 1.92 Gb/s for a frame length of 2304 bits, and achieves savings of 89.13% and 69.83% in power consumption and silicon area over state-of-the-art, with a reduction of 60.5% in interconnect length. 288 byte. Balh-Cocke-Jelinek-Raviv algorithm. Dynamic transport network. Interconnect complexity. Interconnect length. Low-density parity-check decoders. Memory overhead. Memory-efficient decoder. Merged-schedule merge-passing algorithm. Multiple check to-bit message. Optimizations. Power consumption. Routing messages. Scalable message-transport network. Silicon. Soft-input soft-output message update mechanism. Storing. Turbo decoding algorithm. IEEE Transactions on VLSI systems 11, 6 (2003). FO UPD DENG-II Article