00000cab a22000003a 4500 UP-99796217609624629 Buklod 20231007234420.0 m |o d | ta 110119s xx d | ||r ||||| || DENGII eng Xun Liu Design of a 20-mb s 256-state Viterbi decoder. pp. 965-975 The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often consist of long interconnect wires, resulting in large area and high power consumption. In this paper, we propose a data transfer oriented design methodology to implement a low-power 256-state rate-1/3 Viterbi decoder. Our architectural level scheme uses operation partitioning, packing, and scheduling to analyze and optimize interconnect effects in early design stages. In comparison with other published Viterbi decoders, our approach reduces the global data transfers by up to 75% and decreases the amount of global buses by up to 48%, while enabling the use of deeply pipelined datapaths with no data forwarding. In the register-transfer level (RTL) implementation, we apply precomputation in conjunction with saturation arithmetic to further reduce power dissipation with provably no coding performance degradation. Designed using a 0.25 μm standard cell library, our decoder achieves a throughput of 20 Mb/s in simulation and dissipates only 0.45 W. 0.25 micron. 0.45 W. 20 Mbyte. RTL. Data transfer. Global buses. Global communication channels. High-throughput large-state Viterbi decoders. Interconnect effects. Interconnect wires. Parallel processors. Pipelined datapaths. Power dissipation. Register-transfer level implementation. IEEE Transactions on VLSI systems 11, 6 (2003). FO UPD DENG-II Article