00000cab a22000003a 4500 UP-99796217609624610 Buklod 20231007234420.0 m |o d | ta 110119s xx d | ||r ||||| || DENGII eng Taskin, B. Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. pp. 12-27 This paper describes a linear programming (LP) problem formulation applicable to the static-timing analysis of large scale synchronous circuits with level-sensitive latches. Specifically, an LP formulation for the clock period minimization problem is developed. In order to minimize the clock period of level-sensitive circuits, the simultaneous effects of time borrowing and nonzero clock skew scheduling are considered. The clock period minimization problem is formulated for both single-phase and multi-phase clocking schemes. The ISCAS'89 benchmark circuits are used to derive experimental results. LP minimization problems for these benchmark circuits are generated using the modified big M (MBM) method and the generated problems are solved using the industrial LP solver CPLEX . The experimental results demonstrate up to 63% improvements in minimum clock period compared to flip-flop based circuits with zero clock skew. ISCAS89 benchmark circuits. MBM. Big M method. Clock period minimization. Flip-flop based circuits. Industrial LP solver CPLEX. Large scale synchronous circuits. Level sensitive circuits. Level sensitive digital synchronous circuits. Level sensitive latches. Linear programming. Linearization. Multiphase clocking schemes. Nonzero clock skew scheduling. Optimization. Singlephase clocking schemes. Time borrowing. Timing analysis. Zero clock skew. IEEE Transactions on VLSI systems 12, 1 (2004). FO UPD DENG-II Article