APA aipamena

Taskin, B. Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. IEEE Transactions on VLSI systems.

Chicago Style aipamena

Taskin, B. "Linearization of the Timing Analysis and Optimization of Level-sensitive Digital Synchronous Circuits." IEEE Transactions on VLSI Systems .

MLA aipamena

Taskin, B. "Linearization of the Timing Analysis and Optimization of Level-sensitive Digital Synchronous Circuits." IEEE Transactions on VLSI Systems, .