APA引文

Taskin, B. Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. IEEE Transactions on VLSI systems.

Chicago Style (17th ed.) Citation

Taskin, B. "Linearization of the Timing Analysis and Optimization of Level-sensitive Digital Synchronous Circuits." IEEE Transactions on VLSI Systems .

MLA引文

Taskin, B. "Linearization of the Timing Analysis and Optimization of Level-sensitive Digital Synchronous Circuits." IEEE Transactions on VLSI Systems, .

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