Taskin, B. Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. IEEE Transactions on VLSI systems.
Chicago Style (17th ed.) CitationTaskin, B. "Linearization of the Timing Analysis and Optimization of Level-sensitive Digital Synchronous Circuits." IEEE Transactions on VLSI Systems .
MLA引文Taskin, B. "Linearization of the Timing Analysis and Optimization of Level-sensitive Digital Synchronous Circuits." IEEE Transactions on VLSI Systems, .
警告:這些引文格式不一定是100%准確.