APA-viite (7. p.)

Taskin, B. Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. IEEE Transactions on VLSI systems.

Chicago-viite (17. p.)

Taskin, B. "Linearization of the Timing Analysis and Optimization of Level-sensitive Digital Synchronous Circuits." IEEE Transactions on VLSI Systems .

MLA-viite (9. p.)

Taskin, B. "Linearization of the Timing Analysis and Optimization of Level-sensitive Digital Synchronous Circuits." IEEE Transactions on VLSI Systems, .