High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme.

High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme.

Among existing works of high-speed pipelined adaptive decision feedback equalizer (ADFE), the pipelined ADFE using relaxed look-ahead technique results in a substantial hardware saving than the parallel processing or Look-ahead approaches. However, it suffers from both the signal-to-noise ratio (SNR...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on VLSI systems 12, 2 (2004).
Päätekijä: Meng-Da Yang
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
CMOS standard cell.
VLSI design.
Adaptive decision feedback equalizer.
Decision feedback loop.
High-performance VLSI architecture.
Iteration bound.
Output mean-square error.
Pipelined architecture.
Predictive parallel branch slicer.
Prototyping chip.
Relaxed look-ahead DFE.
Sensitivity indexes.