The Chimaera reconfigurable functional unit.

By strictly separating reconfigurable logic from the host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper, we describe Chimaera, a system that overcomes the communication bottleneck by integrating reconfigurable logic into the host proces...

Szczegółowa specyfikacja

Opis bibliograficzny
Wydane w:	IEEE Transactions on VLSI systems 12, 2 (2004).
1. autor:	Hauck, S.
Format:	Artykuł
Język:	English
Hasła przedmiotowe:	Chimaera reconfigurable functional unit. Communication bottleneck. Field-programmable gate arrays. Greedy algorithm. Hardware system. High-performance general-purpose computing. Host processor. Multi-operand instructions. Multi-output functions. Partial run-time reconfiguration. Reconfigurable architectures. Reconfigurable coprocessor. Reconfigurable logic. Reconfiguration time. Routing algorithm. Speculative execution model.