The Chimaera reconfigurable functional unit. - Hauck, S.
By strictly separating reconfigurable logic from the host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper, we describe Chimaera, a system that overcomes the communication bottleneck by integrating reconfigurable logic into the host processor itself. With direct access to the host processor's register file, the system enables the creation of multi-operand instructions and a speculative execution model key to high-performance, general-purpose reconfigurable computing. Chimaera also supports multi-output functions and utilizes partial run-time reconfiguration to reduce reconfiguration time. Combined, the system can provide speedups of a factor of two or more for general-purpose computing, and speedups of 160 or more are possible for hand-mapped applications.
Keywords: Chimaera reconfigurable functional unit; Communication bottleneck; Field-programmable gate arrays; Greedy algorithm; Hardware system; High-performance general-purpose computing; Host processor; Multi-operand instructions; Multi-output functions; Partial run-time reconfiguration; Reconfigurable architectures; Reconfigurable coprocessor; Reconfigurable logic; Reconfiguration time; Routing algorithm; Speculative execution model