Overview of a compiler for synthesizing MATLAB programs onto FPGAs.

This paper describes a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of digital signal processing (DSP) applications written in MATLAB, and automatically generates synthesizable register transfer level (RTL) models and simulation testbenches in VHDL or Verilog. Th...

Szczegółowa specyfikacja

Opis bibliograficzny
Wydane w:	IEEE Transactions on VLSI systems 12, 3 (2004).
1. autor:	Banerjee, P.
Format:	Artykuł
Język:	English
Hasła przedmiotowe:	Altera Stratix FPGAs. DSP designer. MATLAB benchmarks. RTL model. VHDL. Verilog. Xilinx Virtex II. accelFPGA. Behavioral synthesis tool. Digital signal processing applications. Field programmable gate array. High level synthesis. Logic synthesis tools. Place and route tools. Program compiler. Register transfer level model. Simulation testbenches. Very high speed integrated circuit hardware description language.