Overview of a compiler for synthesizing MATLAB programs onto FPGAs. - Banerjee, P.
This paper describes a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of digital signal processing (DSP) applications written in MATLAB, and automatically generates synthesizable register transfer level (RTL) models and simulation testbenches in VHDL or Verilog. The RTL models can be synthesized using commercial logic synthesis tools and place and route tools onto field-programmable gate arrays (FPGAs). This paper describes how powerful directives are used to provide high-level architectural tradeoffs for the DSP designer. Experimental results are reported on a set of eight MATLAB benchmarks that are mapped onto the Xilinx Virtex II and Altera Stratix FPGAs.
Keywords: Altera Stratix FPGAs; DSP designer; MATLAB benchmarks; RTL model; VHDL; Verilog; Xilinx Virtex II; accelFPGA; Behavioral synthesis tool; Digital signal processing applications; Field programmable gate array; High level synthesis; Logic synthesis tools; Place and route tools; Program compiler; Register transfer level model; Simulation testbenches; Very high speed integrated circuit hardware description language