Memory energy minimization by data compression algorithms, architectures and implementation.

Memory energy minimization by data compression algorithms, architectures and implementation.

Storing data in compressed form is becoming common practice in high-performance systems, where memory bandwidth constitutes a serious bottleneck to program execution speed. In this paper, we suggest hardware-assisted data compression as a tool for reducing energy consumption of processor-based syste...

詳細記述

書誌詳細
出版年:IEEE Transactions on VLSI systems 12, 3 (2004).
第一著者: Benini, L.
フォーマット: 論文
言語:English
主題:
Benchmark programs.
Cache lines.
Cache refills.
Cache-to-memory path.
Compression/decompression unit.
Core based system.
Data statistics.
Embedded systems.
Energy consumption reduction.
General purpose systems.
Hardware assisted data compression.
Hardware implementation.
High performance systems.
Memory bandwidth.
Memory energy minimization.
Offline data profiling.
On-the-fly data compression.
On-the-fly data decompression.
Processor based systems.
Profile driven compression.
Program execution speed.
Table based compression.