DCG deterministic clock-gating for low-power microprocessor design.

DCG deterministic clock-gating for low-power microprocessor design.

With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Because clock power can be significant in high-performance processors, we propose a deterministic clock-gating (DCG) technique which...

Ausführliche Beschreibung

Bibliographische Detailangaben
Veröffentlicht in:IEEE Transactions on VLSI systems 12, 3 (2004).
1. Verfasser: Hai Li
Format: Artikel
Sprache:English
Schlagworte:
D-cache wordline decoders.
DCG.
Bus drivers.
Clock power reduction.
Deterministic clock gating.
Execution units.
High performance processors.
Low power microprocessor design.
Pipeline latches.
Pipelined stages.
Power dissipation.
Superscalar microarchitecture.