Power-delay product minimization in high-performance 64-bit carry-select adders.

Power-delay product minimization in high-performance 64-bit carry-select adders.

This paper analyzes methods to minimize the power-delay product of 64-bit carry-select adders intended for high-performance and low-power applications. A first realization in 0.18-μm partially depleted (PD) silicon-on-insulator (SOI), using complex branch-based logic (BBL) cells, results in a delay...

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Bibliographic Details
Published in:IEEE Transactions on VLSI systems 12, 3 (2004).
Main Author: Neve, A.
Format: Article
Language:English
Subjects:
0.13 micron.
0.18 micron.
1.1 V.
1.5 V.
23 mW.
326 ps.
64 bit.
64 bit carry select adders.
720 ps.
96 mW.
Automatic tuning.
Complex branch based logic cells.
Global carry network.
Low power applications.
Optimization.
Power delay product minimization.
Power dissipation.
Silicon-on-insulator.
Stack height.
Transistor widths.