Interconnect-based system-level energy and power prediction to guide architecture exploration.

Interconnect-based system-level energy and power prediction to guide architecture exploration.

We present a novel technique to predict energy and power consumption in an electronic system, given its behavioral specification and library components. The early prediction gives circuit designers the freedom to make numerous high-level choices (such as die size, package type, and latency of the pi...

詳細記述

書誌詳細
出版年:IEEE Transactions on VLSI systems 12, 4 (2004).
第一著者: Wadekar, S.A
フォーマット: 論文
言語:English
主題:
Architecture exploration.
Behavioral specification.
Die size.
Energy consumption prediction.
Interconnect-based prediction.
Library components.
Package type.
Pipeline latency.
Power consumption prediction.
System level prediction.