Global interconnect design in a three-dimensional system-on-a-chip.

Global interconnect design in a three-dimensional system-on-a-chip.

A stochastic model for the global net-length distribution of a three-dimensional system-on-a-chip (3D-SoC) is derived. Using the results of this model, a global interconnect design window for a 3D-SoC is established by evaluating the constraints of: 1) wiring area; 2) clock wiring bandwidth; and 3)...

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Detalhes bibliográficos
Publicado no:IEEE Transactions on VLSI systems 12, 4 (2004).
Autor principal: Joyner, J.W
Formato: Artigo
Idioma:English
Assuntos:
Clock wiring bandwidth.
Crosstalk noise.
Global interconnect design.
Global net-length distribution.
Global wiring.
Integrated circuit interconnection.
Maximum clock frequency.
Minimum aspect ratio.
Minimum pitch.
Minimum rectilinear Steiner tree length.
Stochastic model.
Three-dimensional system-on-a-chip.
Wiring area.