TY  - JOUR
T1  - A new maximal diagnosis algorithm for interconnect test.
JF  - IEEE Transactions on VLSI systems
A1  - Yongjoon Kim
LA  - English
UL  - https://tuklas.up.edu.ph/Record/UP-99796217609624488
AB  - Interconnect test for highly integrated environments becomes more important in terms of its test time and a complete diagnosis, as the complexity of the circuit increases. Since the board-level interconnect test is based on boundary scan technology, it takes a long test time to apply test vectors serially through a long scan chain. Complete diagnosis is another important issue. Since the board-level test is performed for repair, noticing the faulty position is an essential element of any interconnect test. Generally, the interconnect test algorithms that need a short test time cannot perform the complete diagnosis and the algorithms that perform the complete diagnosis need a lengthy test time. To overcome this problem, a new interconnect test algorithm is developed. The new algorithm can provide the complete diagnosis of all faults with a shorter test time compared to the previous algorithms.
KW  - Board-level test.
KW  - Boundary scan technology.
KW  - Circuit complexity.
KW  - Diagnosis algorithm.
KW  - Fault diagnosis.
KW  - Interconnect test.
ER  -