Systematic IEEE rounding method for high-speed floating-point multipliers.

Systematic IEEE rounding method for high-speed floating-point multipliers.

For performance reasons, many high-speed floating-point multipliers today precompute multiple significand values (SVs) in advance. The final normalization and rounding steps are then performed by selecting the appropriate SV. While having speed advantages, this integrated rounding method complicates...

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Pubblicato in:IEEE Transactions on VLSI systems 12, 5 (2004).
Autore principale: Quach, N.T
Natura: Articolo
Lingua:English
Soggetti:
IEEE rounding method.
Hardware implementation.
Hardware optimization.
High speed floating point multipliers.
Integrated rounding method.
Multiple significand values.
Precomputation.
Prediction scheme.
Rounding digits selection.
Rounding logic.
Rounding table.