Modeling subthreshold SOI logic for static timing analysis.

Modeling subthreshold SOI logic for static timing analysis.

A simple, yet realistic physics-based model is introduced to describe the subthreshold drain current of a MOSFET taking into account the body- and drain-voltage dependencies, including the short channel effects. This model, verified by SPICE simulations, describes adequately the pseudotriode and pse...

Szczegółowa specyfikacja

Opis bibliograficzny
Wydane w:IEEE Transactions on VLSI systems 12, 6 (2004).
1. autor: Valentian, A.
Format: Artykuł
Język:English
Hasła przedmiotowe:
CMOS digital integrated circuits.
MOSFET.
SOI logic.
SPICE simulations.
Analytical expressions.
Complementary metal-oxide-semiconductor.
Integrated circuit modelling.
Logic delay.
Logic switching.
Low-power electronics.
Metal-oxide-semiconductor field effect transistor.
Pseudosaturation regions.
Pseudotriode regions.
Short channel effect.
Silicon on insulator logic.
Simulation program with integrated circuit.
Static timing analysis.
Subthreshold drain current.