Dyfyniad APA

Valentian, A. Modeling subthreshold SOI logic for static timing analysis. IEEE Transactions on VLSI systems.

Dyfyniad Arddull Chicago

Valentian, A. "Modeling Subthreshold SOI Logic for Static Timing Analysis." IEEE Transactions on VLSI Systems .

Dyfyniad MLA

Valentian, A. "Modeling Subthreshold SOI Logic for Static Timing Analysis." IEEE Transactions on VLSI Systems, .

Rhybudd: Mae'n bosib nad yw'r dyfyniadau hyn bob amser yn 100% cywir.