APA (7th ed.) Citation

Valentian, A. Modeling subthreshold SOI logic for static timing analysis. IEEE Transactions on VLSI systems.

Chicago Style (17th ed.) Citation

Valentian, A. "Modeling Subthreshold SOI Logic for Static Timing Analysis." IEEE Transactions on VLSI Systems .

MLA (9th ed.) Citation

Valentian, A. "Modeling Subthreshold SOI Logic for Static Timing Analysis." IEEE Transactions on VLSI Systems, .

Warning: These citations may not always be 100% accurate.