Low-latency architectures for high-throughput rate Viterbi decoders.
In this paper, a novel K-nested layered look-ahead method and its corresponding architecture, which combine K-trellis steps into one trellis step (where K is the encoder constraint length), are proposed for implementing low-latency high-throughput rate Viterbi decoders. The proposed method guarantee...
| में प्रकाशित: | IEEE Transactions on VLSI systems 12, 6 (2004). |
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| मुख्य लेखक: | |
| स्वरूप: | लेख |
| भाषा: | English |
| विषय: |