TY  - JOUR
T1  - Implicit deductive fault simulation for complex delay fault models.
JF  - IEEE Transactions on VLSI systems
A1  - Deodhar, J.V
LA  - English
UL  - https://tuklas.up.edu.ph/Record/UP-99796217609624462
AB  - This paper introduces an implicit version of the well-known deductive fault simulation technique suitable to delay fault models with an exponential number of faults. The proposed method calculates the fault coverage by generating lists of entities for each line during a single topological circuit traversal. Each stored entity only contains a number and a subset of the test vectors. No delay faults are stored, and no special data structures are required. There are significant differences between the presented implicit method and fault coverage using deductive fault simulation. The method is shown to be effective for delay the path and segment delay fault models.
KW  - Data structures.
KW  - Fault coverage.
KW  - Implicit deductive fault simulation.
KW  - Path delay fault models.
KW  - Segment delay fault model.
KW  - Subset.
KW  - Topological circuit traversal.
ER  -