Efficient metrics and high-level synthesis for dynamically reconfigurable logic.

Efficient metrics and high-level synthesis for dynamically reconfigurable logic.

The increase in complexity of programmable hardware platforms results in the need to develop efficient high-level synthesis (HLS) tools since it allows more efficient exploration of the design space while predicting the effects of technology specific tools on the design space. Much of the previous w...

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Pubblicato in:IEEE Transactions on VLSI systems 12, 6 (2004).
Autore principale: Meribout, M.
Natura: Articolo
Lingua:English
Soggetti:
DRL LSI circuit.
Configurable logic blocks.
Dynamic reconfigurable circuits.
Dynamic reconfigurable logic.
Functional units.
High-level synthesis tools.
Interconnect-sensitive synthesis.
Interconnects.
Multiplexer.
Programmable hardware platforms.