Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling.

Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling.

The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for the case of combinational designs. The problem is NP-hard in general. To address the problem in the case of synchronous sequen...

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Publicat a:IEEE Transactions on VLSI systems 12, 6 (2004).
Autor principal: Chabini, N.
Format: Article
Idioma:English
Matèries:
NP-hard problem.
Combinational circuits.
Computational elements.
Dynamic power consumption.
Minimal clock period.
Polynomial run time.
Polynomial time algorithms.
Single phase design.
Supply voltage scaling.
Synchronous sequential digital design.