Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling.

The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for the case of combinational designs. The problem is NP-hard in general. To address the problem in the case of synchronous sequen...

Szczegółowa specyfikacja

Opis bibliograficzny
Wydane w:IEEE Transactions on VLSI systems 12, 6 (2004).
1. autor: Chabini, N.
Format: Artykuł
Język:English
Hasła przedmiotowe: