Chabini, N. Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling. IEEE Transactions on VLSI systems.
Citace podle Chicago (17th ed.)Chabini, N. "Reducing Dynamic Power Consumption in Synchronous Sequential Digital Designs Using Retiming and Supply Voltage Scaling." IEEE Transactions on VLSI Systems .
Citace podle MLA (9th ed.)Chabini, N. "Reducing Dynamic Power Consumption in Synchronous Sequential Digital Designs Using Retiming and Supply Voltage Scaling." IEEE Transactions on VLSI Systems, .
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