Chabini, N. Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling. IEEE Transactions on VLSI systems.
Chicago Style (17th ed.) CitationChabini, N. "Reducing Dynamic Power Consumption in Synchronous Sequential Digital Designs Using Retiming and Supply Voltage Scaling." IEEE Transactions on VLSI Systems .
MLA (9th ed.) CitationChabini, N. "Reducing Dynamic Power Consumption in Synchronous Sequential Digital Designs Using Retiming and Supply Voltage Scaling." IEEE Transactions on VLSI Systems, .
Warning: These citations may not always be 100% accurate.