Chabini, N. Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling. IEEE Transactions on VLSI systems.
توثيق أسلوب شيكاغو (الطبعة السابعة عشر)Chabini, N. "Reducing Dynamic Power Consumption in Synchronous Sequential Digital Designs Using Retiming and Supply Voltage Scaling." IEEE Transactions on VLSI Systems .
توثيق جمعية اللغة المعاصرة MLA (الإصدار التاسع)Chabini, N. "Reducing Dynamic Power Consumption in Synchronous Sequential Digital Designs Using Retiming and Supply Voltage Scaling." IEEE Transactions on VLSI Systems, .
تحذير: قد لا تكون هذه الاستشهادات دائما دقيقة بنسبة 100%.