Tight integration of timing-driven synthesis and placement of parallel multiplier circuits.

In deep submicrometer (DSM) design, the interconnect delay becomes equally as or more important than that of logic gates. In particular, to achieve timing closure in DSM design, it is essential to consider the interconnect delay at an early stage of the synthesis process. Unfortunately, few successe...

詳細記述

書誌詳細

出版年:	IEEE Transactions on VLSI systems 12, 7 (2004).
第一著者:	Shin, K.
フォーマット:	論文
言語:	English
主題:	Benchmark design. Circuit placement. Circuit structure. Circuit timing. Computation time. Interconnect delay. Interconnect topology. Layout effect. Parallel multiplier circuit. Timing driven relocation. Timing driven synthesis. Timing optimal FA tree allocation.