APA citiranje

Shin, K. Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. IEEE Transactions on VLSI systems.

Chicago Style (17th ed.) Citation

Shin, K. "Tight Integration of Timing-driven Synthesis and Placement of Parallel Multiplier Circuits." IEEE Transactions on VLSI Systems .

MLA citiranje

Shin, K. "Tight Integration of Timing-driven Synthesis and Placement of Parallel Multiplier Circuits." IEEE Transactions on VLSI Systems, .