Ozev, S. Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead. IEEE Transactions on VLSI systems.
Citace podle Chicago (17th ed.)Ozev, S. "Design of Concurrent Test Hardware for Linear Analog Circuits with Constrained Hardware Overhead." IEEE Transactions on VLSI Systems .
Citace podle MLA (9th ed.)Ozev, S. "Design of Concurrent Test Hardware for Linear Analog Circuits with Constrained Hardware Overhead." IEEE Transactions on VLSI Systems, .
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