Ozev, S. Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead. IEEE Transactions on VLSI systems.
Chicago Style (17th ed.) CitationOzev, S. "Design of Concurrent Test Hardware for Linear Analog Circuits with Constrained Hardware Overhead." IEEE Transactions on VLSI Systems .
MLA (9th ed.) CitationOzev, S. "Design of Concurrent Test Hardware for Linear Analog Circuits with Constrained Hardware Overhead." IEEE Transactions on VLSI Systems, .
Warning: These citations may not always be 100% accurate.