Ozev, S. Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead. IEEE Transactions on VLSI systems.
Citazione stile Chigago Style (17a edizione)Ozev, S. "Design of Concurrent Test Hardware for Linear Analog Circuits with Constrained Hardware Overhead." IEEE Transactions on VLSI Systems .
Citatione MLA (9a ed.)Ozev, S. "Design of Concurrent Test Hardware for Linear Analog Circuits with Constrained Hardware Overhead." IEEE Transactions on VLSI Systems, .
Attenzione: Queste citazioni potrebbero non essere precise al 100%.