APA aipamena

Ozev, S. Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead. IEEE Transactions on VLSI systems.

Chicago Style aipamena

Ozev, S. "Design of Concurrent Test Hardware for Linear Analog Circuits with Constrained Hardware Overhead." IEEE Transactions on VLSI Systems .

MLA aipamena

Ozev, S. "Design of Concurrent Test Hardware for Linear Analog Circuits with Constrained Hardware Overhead." IEEE Transactions on VLSI Systems, .