Double sampling data checking technique an online testing solution for multisource noise-induced errors on on-chip interconnects and buses.

Double sampling data checking technique an online testing solution for multisource noise-induced errors on on-chip interconnects and buses.

With processors and system-on-chips using nano-meter technologies, several design and test efforts have been recently developed to eliminate and test for many emerging DSM noise effects. In this paper, we show the emergence of multisource noise effects, where multiple DSM noise sources combine to pr...

詳細記述

書誌詳細
出版年:IEEE Transactions on VLSI systems 12, 7 (2004).
第一著者: Yi Zhao
フォーマット: 論文
言語:English
主題:
SOI.
Bus design.
Double sampling data checking circuit.
Functional error.
Interconnect.
Multisource noise effects.
Nanotechnology.
Online detection circuit.
Online testing.
System on chips.
Timing error.