An architecture and compiler for scalable on-chip communication.

A dramatic increase in single chip capacity has led to a revolution in on-chip integration. Design reuse and ease of implementation have became important aspects of the design process. This paper describes a new scalable single-chip communication architecture for heterogeneous resources, adaptive sy...

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Publié dans:IEEE Transactions on VLSI systems 12, 7 (2004).
Auteur principal: Jian Liang
Format: Article
Langue:English
Sujets: