An architecture and compiler for scalable on-chip communication.

An architecture and compiler for scalable on-chip communication.

A dramatic increase in single chip capacity has led to a revolution in on-chip integration. Design reuse and ease of implementation have became important aspects of the design process. This paper describes a new scalable single-chip communication architecture for heterogeneous resources, adaptive sy...

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Detalhes bibliográficos
Publicado no:IEEE Transactions on VLSI systems 12, 7 (2004).
Autor principal: Jian Liang
Formato: Artigo
Idioma:English
Assuntos:
0.18 micron.
400 MHz.
Doppler radar processor.
MPEG-2 video encoder.
SOC communication.
VLSI.
Adaptive SOC.
Adaptive system-on-a-chip.
Clock rate.
Compile time scheduled communication.
Hierarchical bus based system-on-chip.
High bandwidth signal processing application.
Mapping technology.
On-chip integration.
Scalable on-chip communication.
Scalable single-chip communication architecture.