Designing an asynchronous microcontroller using Pipefitter.

This paper discusses how Pipefitter, a tool chain that implements a fully automated synthesis flow for asynchronous circuits, can be used to design a simple asynchronous microcontroller. The use of register transfer level (RTL)-like Verilog hardware description languages (HDL) as the input format ma...

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Vydáno v:	IEEE Transactions on VLSI systems 12, 7 (2004).
Hlavní autor:	Blunno, I.
Médium:	Článek
Jazyk:	English
Témata:	HDL. Application specific integrated circuit. Asynchronous circuit. Asynchronous microcontroller. Automated insertion. Design flow. Genetic algorithm. Logic design. Matched delay. Multiplexer optimization. Pipefitter. Register transfer level. Standard cell based layout tool. State of the art. Synchronous RTL. Timing analysis. Verilog hardware description languages.